The present invention relates to integrated circuit structures and fabrication methods, especially to silicided polysilicon gates.
Background: Gate Resistance
Even as the size of integrated circuits shrinks, the demand for higher performance, including decreased resistance on conductive lines, increases. In logic integrated circuits, polysilicon gate lines commonly use a self-aligned metal silicide, such as titanium silicide, to reduce gate resistance and gate propagation delay. As device sizes shrink, smaller gate sizes mean that there are fewer nucleation centers for the transformation of titanium disilicide from a high resistance state (C49) to a low resistance state (C54), giving less desirable results. Further background in silicided gate structures can be found in Silicon Processing for the VLSI Era, Wolf et al., 1986 (see especially Volume 1, Chapter 11 on "Refractory Metals and Their Silicides in VLSI Fabrication" and Volume 2, Chapter 3 on "Contact Technology and Local Interconnects for VLSI"), which is hereby incorporated by reference.
U.S. Pat. No. 5,196,360 (Doan et al.) shows a previous method of forming a silicide on a gate structure. This patent discloses a polysilicon gate with dielectric sidewalls which "extend vertically upward from the source an [sic] drain regions . . . to somewhat below the uppermost surface of the gate electrode region". Although this will leave a small portion of the gate sidewall exposed for silicidation, the process shown uses sputter deposition (PVD) to deposit the metal layer which will be converted into a silicide. Since sputter deposition gives very poor step coverage, this method would not give effective silicide coverage on the sidewalls of the gate. Furthermore, this patent appears to view silicide growth on the sidewalls of the gate as a problem which must be dealt with, rather than a desirable effect.
A commonly owned application (provisional No. 60/045,178, filed Apr. 30, 1997) describes a process in which the height of the sidewall spacers is reduced, so that metal can be deposited along a significant height of the sidewalls for the gate, as well as on top of the gates. In the prior application, this is suggested as a way of reducing the total resistance of a gate line, by in effect reducing the average resistivity of the material, and by changing the overall line-to-phase ratio of the gate pattern, but this prior application still uses gate sidewalls to provide separation between the silicide layer on the gate structure and the silicide on the conductive part of the source/drain regions.
Background: Drain Profile Engineering
One of the long-standing problems in small field effect transistors is hot carrier effects. When a conventional MOS transistor structure is scaled down to one micron or less, the potential energy of an electron changes dramatically when it hits the N+drain boundaries. This sudden change in potential energy in a short distance creates a high electric field. This is undesirable because it causes the electrons to behave differently within the semiconductor lattice. Electrons which have been activated by high electric fields are referred to as "hot electrons", and can, for example, penetrate into or through the gate dielectric. Electrons which penetrate into, but not through, the gate dielectric can cause the gate dielectrics to become charged up over time. Thus, the behavior of the transistor will gradually shift in the field, until the transistor may fail in service. This is extremely undesirable. Holes are also subject to the effects of a high electric field, although this is usually not quite as great a concern with holes, due to their higher effective mass in silicon.
To avoid hot carrier effects, several techniques have been proposed. One of these techniques is lightly doped drain extension regions, or "LDD" regions. In this structure, which is now used in most small-dimension transistors, a first light and shallow implant is performed before sidewall spacers are formed on the gate structure. After the sidewall spacers are in place; a second heavier implant is performed. The first implant provides only a relatively low conductivity in the silicon, so that the voltage has a significant gradient across the LDD region. This prevents the voltage difference, between channel and drain, from appearing entirely at the drain boundary. By increasing the distance over which this voltage difference occurs, the peak electric field is reduced, and this tends to reduce channel hot carrier (CHC) effects. Another conventional technique which has been used is the "double doped drain." In this technique, the drain is implanted with both phosphorus and arsenic (or alternatively with both phosphorus and antimony.) Phosphorus diffuses faster, at a given temperature, than arsenic, and thus produces a slightly "fuzzy" drain profile. Again, this has the effect of stretching the voltage change at the drain boundaries, and this reduces the peak electric field, as is desirable.
Another common technique, which is not done primarily for reasons of drain profiling, but which has some influence on this, is the "smiling" oxidation. After a gate structure has been formed, a further oxidation is commonly performed, to widen the oxide thickness at the lower corners of the gate. This has the effect of slightly increasing the separation between the lower corners of the gate and the silicon substrate. This is desirable, since the electric field is slightly higher at the gate corners, due to geometric effects. This is usually done, however, primarily to compensate for any damage to the gate dielectric at the lower gate corners which may be caused by etching processes.
Enhancements to Gate Conductivity and Drain Profile Engineering
The present application provides several innovations which are aimed at optimizing the conductivity of gate structures, and also provide new tools for drain profiles engineering.
Preferably, in one embodiment of the disclosed method, an oxidation resistant sidewall layer is applied to the gate structure, to permit a "smiling" oxidation be performed to elevate the corners of the gate structure. The sidewalls of the gate are then exposed and a metal for siliciding is deposited overall, after which source/drain implants are performed. Optionally, additional source/drain implants can be performed prior to metal deposition. After an implant has been done through the metal, an annealing step is applied, to cause silicidation, and also to activate the implant into the source/drain regions. The unreacted metal is then stripped, providing a polysilicon gate which is heavily coated with silicide. If desired, additional dielectric sidewall layers can be added onto the silicide sidewalls after the metal is stripped, to assure a safe offset between the silicide and the drain siliciding. If desired, the source/drains can be silicided separately from the gates, to provide, e.g., two different silicide compositions on the source/drains and on the gates.
Preferably, in another embodiment of the disclosed method, after a smiling oxidation is performed and the nitride sidewalls removed, the sidewalls of the gate structure are extended by a conformal polysilicon deposition. Thus, the location of the smiling oxidation does not have to be aligned to the corners of the gate, as has conventionally been desired. This -opens up a new range of options in drain profile engineering. The gate-induced electric field can be removed from the drain region, by an amount which is independent of the separation between N+ and N- (or alternatively P+ and P-) diffusions.
Advantages of the disclosed methods and structures include:
increased gate conductivity; PA0 additional control over gate corner profiles; PA0 additional control over gate electric fields; PA0 additional control over silicided gate structures; PA0 additional control over the line-to-space ratio of the gate pattern; and PA0 uses conventional processes.